The present invention relates to an interface between a processor and other subsystems in a computer system. More particularly, the present invention relates to an adaptive processor interface which is operable with a number of different types of processors, depending on a select input to the interface.
A computer system typically includes a microprocessor and a number of subsystems. Examples of subsystems used in a computer system include a memory subsystem and an input/output (I/O) bus subsystem. The memory subsystem commonly includes a block of dynamic random access memory (DRAM). The block of DRAMs stores a wide variety of information used to support the computer system.
The I/O bus subsystem includes an I/O bus which provides the processor with access to other devices external to the computer system such as memory devices, slave-type devices, or other processors. One typical I/O bus is the Micro Channel bus manufactured by International Business Machines Corp. of Armonk, N.Y.
In addition to the memory subsystem and the I/O bus subsystem, a computer system also typically includes some type of processor interface between the microprocessor and the subsystems. The interface provides communication between the processor and the various subsystems in the computer system. In the case of a computer system having a memory subsystem and an I/O bus subsystem, the interface provides communication between the processor and the I/O bus, as well as between the processor and memory devices in the memory subsystem.
Such interfaces typically include bus controller circuitry for acquiring control of the I/O bus, and for providing timing control between the I/O bus and the processor. The bus controller circuitry receives processor request signals from the processor such as command signals, address signals and data signals which represent a requested I/O bus operation. The bus controller circuitry then controls the I/O bus in accordance with those processor request signals to accomplish the requested operation.
The interface also typically includes a memory controller which provides timing control between the processor and the memory devices. The memory controller receives processor request signals, such as command signals, address signals and data signals from the processor which represent a requested memory operation. The memory controller then controls the memory devices based on those processor request signals to accomplish the requested operation.
For the sake of the present disclosure, the term "processor request signal" or "processor request signals" includes information which is provided by the processor to request a desired operation. A processor request signal can go by different names in the industry, depending on the different processor type being used. For example, when using an Intel 80486 processor, processor request signals preferably include the Address Strobe Signal (ADS) which marks a point in time when a request is being made by the 486 processor. The processor request signals also include the Status signals which define a type of operation which is being requested. Such signals include the Memory-I/O signal, the Read/Write signal, the Data/Code signal and other such signals. The processor request signals also include address signals which identify the location where the requested operation is to take place. Further, the processor request signals include Byte Enable signals which identify the specific byte on which the system is to operate. All of these types of signals, as well as any other signals provided by the 486 type processor to define or request an operation, are included as processor request signals.
In the past, processor interfaces for controlling subsystems were designed to interface the subsystems to one specific processor type. For example, the processor interface may typically be crafted around a specific Intel type processor having a 16 bit bus, or a specific Motorola type processor having a 16 bit bus. The processor interface would be designed to accept processor request signals unique to the specific processor type and decode those request signals into the desired memory request signals or I/O bus control signals to accomplish the requested operation.
However, such a processor interface requires those selling chip sets embodying the interface to qualify and stock a different chip set for each processor type. This results in those selling such chip sets to carry excess inventory which can be very costly. Further, those selling such chip sets must also qualify a large number of different types of chip sets. The qualification process can be very time consuming and costly as well. Both of these factors contribute to inefficiency which increases the cost of the chip sets to the ultimate consumer.